1. Field of the Invention
The present invention relates to a one-chip microcomputer having a plurality of peripheral circuits integrated together with a central processing unit and others on a single chip, and more specifically to a low power consumption one-chip microcomputer of this type.
2. Description of Related Art
In general purpose one-chip microcomputers, not only a central processing unit (CPU) and memories, but also various kinds of peripheral circuits including an AfD converter, a D/A converter, a timer, a serial interface and others for complying with various applications, are formed on a single chip.
Signals for controlling these various kinds of peripheral circuits formed on the microcomputer chip, include a clock signal generated in a clock generator for controlling an operation timing of each peripheral circuit, and a strobe signal generated in the CPU for controlling a timing of a data read/write operation to the peripheral circuits.
Referring to FIG. 1, there is shown a block diagram of one example of a conventional microcomputer including four peripheral circuits.
In the microcomputer shown in FIG. 1, a clock generator 1 generates a clock signal 2, which is supplied unconditionally and commonly to a central processing unit (CPU) 3 and all of four peripheral circuits 41, 42, 43 and 44. The clock signal 2 is used as a time reference, on the basis of which the operation order in time and the operation timing of the CPU 3 and the four peripheral circuits 41, 42, 43 and 44 are determined.
The CPU 3 and the four peripheral circuits 41, 42, 43 and 44 are coupled to each other through an address/data bus 5, and the CPU 3 supplies a strobe signal 6 to all of the four peripheral circuits 41, 42, 43 and 44 for the purpose of controlling a timing of the data read/write operation to the peripheral circuits 41, 42, 43 and 44. Accordingly, the timing of the data read/write operation of the CPU 3 to the peripheral circuits 41, 42, 43 and 44 is determined by this strobe signal 6.
In general, as mentioned above, the conventional general purpose microcomputer includes a plurality of peripheral circuits of various types formed on the single chip, in order to make it possible for the microcomputer to be used in different applications. In fact, however, when this general purpose microcomputer is used in an actual application system, all of the peripheral circuits formed on the microcomputer chip are not necessarily used.
Therefore, unconditional continuous application of the clock 2 and the strobe signal 6 to all of the peripheral circuits means that the clock and the strobe signal are applied to the peripheral circuits which are not used in the actual application system, and therefore, electric power is wastefully consumed.
Japanese Patent Application Laid-open Publication JP-A-60-195631 has disclosed a data processing system configured to reduce a wasteful electric power consumption. This data processing system is constructed to selectively supply a clock signal to peripheral circuits in accordance with a control signal from a CPU. For this purpose, the clock signal is applied to each of the peripheral circuits through a corresponding AND gate controlled by the control signal supplied from the CPU.
In initialization of a data processing program, the control signals to be respectively supplied to the peripheral circuits which are not used in the actual application system, are set to "0", so that the application of the clock to these peripheral circuits not to be used is inhibited, and on the other hand, the control signals to be respectively supplied to the peripheral circuits which are used in the actual application system, are set to "1", so that the clock is supplied to these peripheral circuits to be used.
Furthermore, Japanese Patent Application Laid-open Publication JP-A-61-285521 has proposed a low power consumption microcomputer, which includes a gate for on-off controlling the application of the clock to peripheral circuits coupled to the microcomputer, and a clock signal control means for putting the above mentioned gate into an off condition when each peripheral circuit does not actually operate, and for opening the above mentioned gate only when each peripheral circuit actually operates so that the clock is actually supplied to the peripheral circuits. Thus, on the basis of a program, the peripheral circuits are controlled to be selectively put into the operating condition.
Furthermore, a reset signal is applied to a designated peripheral circuit at a designated timing, so that, in a peripheral circuit of the type requiring a clock for the purpose of maintaining an initialized condition after resetting, it is possible to reduce the electric power consumption caused by the clock application after the reset inputting until the peripheral circuit is actually used, whereby a lower power consumption computer can be realized.
In addition, Japanese Patent Application Laid-open Publication JP-A-64-86224 shows a stand-by circuit for a microcomputer, which is configured so that, not only a CPU but also peripheral circuits can be selectively stopped when the system is put into a stand-by mode by executing a clock stop instruction in the process of a program execution by a CPU. For this purpose, a peripheral hardware controlling circuit is provided, which receives hardware stop information included in the clock stop instruction from the CPU, and selectively supplies a dock stop signal to a plurality of peripheral hardware, for the purpose of reducing the electric power consumption in the stand-by mode.
On the other hand, it is very significant to reduce the power consumption of the microcomputer, in particular in a battery cell driven, microcomputer-controlled, small-sized apparatus, such as a portable telephone and a camera.
In the microcomputer shown in FIG. 1, since the clock and the strobe signal are supplied to the peripheral circuits which are never used in the actual application system, the wasteful electric power consumption is inevitable. However, all the data processing systems proposed in the above mentioned Japanese patent application publications for overcoming this drawback are so constructed that, for realizing a lower power consumption, the application of the clock to the peripheral circuits is on/off-controlled in accordance with a program of the CPU. However, it is actually difficult to easily change the setting of the use or non-use of each peripheral circuit, since it causes possibility of an error in the program, and hence, in the programmed operation, and therefore, there is a possibility of losing reliability of the system. In fact, there is almost no case in which the peripheral circuits used in the system are dynamically switched over in the course of a program execution.
Furthermore, the method of reducing the electric power consumption caused by the clock required for maintaining the initialized condition by realizing the reset input in a programmed operation and rendering off the clock used in the peripheral circuits, is effective only for some peripheral circuits requiring the clock for maintaining the initialized condition, and only when the microcomputer system starts to be used or operated. Therefore, a large advantage cannot be expected if the whole of the microcomputer is considered and if the whole of the use time is considered.
In addition, all of the above mentioned low power consumption data processing systems are constructed to control on-off of only application of the clock to the peripheral circuits, and therefore, to unconditionally continuously supply various strobe signals to an address register, data registers and the like. Because of this, the electric power consumption cannot be satisfactorily reduced.
Furthermore, provision in the program of a special clock stop control instruction for controlling the stoppage of the application of the clock to the peripheral circuits, results in an increase of circuit elements such as an instruction decoder in the CPU.